The present invention relates to a semiconductor device including a plurality of chips, and more particularly to a semiconductor device having a calibration circuit operable to adjust an impedance of an output circuit.
There has been known a calibration circuit connected to a ZQ terminal as one of external terminals of a semiconductor device. The calibration circuit adjusts the impedance of an output circuit connected to another external terminal, such as a DQ terminal, with use of an external resistance element connected to the ZQ terminal. For example, JP-A-2011-101143 discloses this type of circuit at FIG. 1.
There also has been known a semiconductor device having a plurality of semiconductor chips stacked together. The semiconductor chips are electrically connected to each other by through electrodes (through silicon vias; TSVs) extending through each of the semiconductor chips. For example, JP-A 2011-029535 discloses this type of semiconductor device at FIG. 4.